EDA design based on FPGA engineering

Take the QuartusII13.0EDA software as an example to introduce the EDA design flow of Verilog text input. 1. First create a new folder on the D drive or G drive, etc., and name it with English letters, for example, create a folder SY1. FPGA project directory: dev: project is

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FPGA can not synthesize statement related knowledge

Hello, everyone, and it's time for a day of study. Today, we'll talk about the non-synthetic statements in FPGA. (1) Structures supported by all synthesis tools: always, assign, begin, end, case, wire, tri, auply0, supply1, reg, integer, default, for, function,

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