I have been thinking about writing code recently. Can I write this comprehensively? Always do not worry, or write a problem when the synthesis, is very troublesome, although read some books, such as blocking the assignment of combinatorial logic, timing with non-blocking assignment, delay can not be integrated, etc., but No one can fully understand all the problems! I saw this article inadvertently today. It seems that it is still judged by experience whether it is synthesizable! I hope that one day I will have a detailed understanding of the commonly used comprehensive problems!

First, HDL is not a hardware design language In the past, I have encountered many VHDL or Verilog HDL beginners to ask some similar questions, such as how to achieve division, root number, how to write loop statements and so on. In this forum, I also often see some netizens asking questions of this kind.
For these issues, the first thing to be clear is that VHDL and Veriglog are not languages ​​developed for hardware design, but we are currently using them to design hardware. HDL is an abbreviation of Hardware DescripTIon Language, and the official Chinese name is "Hardware Description Language". In other words, HDL is not a "Hardware Design Language." Don't look at this word, it is this word that determines that most circuit designs must follow the RTL pattern to write code, and not just write lexical-compliant HDL code.

Second, the reason why the origin of HDL is "hardware description language", we must start from the origin of HDL.

VHDL began development in 1980 under the direction of the US Department of Defense, completed in 1983, and became the IEEE standard in 1987. The language was originally developed because of the need for the US Department of Defense to purchase electronic equipment. US military equipment is purchased from private companies and often faces the risk of re-production, repair, and repair of a weapon if a certain weapon is heavily equipped with troops and a supplier of one of the parts fails a few years later. There will be big problems with maintenance. The internal structure of electronic equipment, especially integrated circuits, is more complicated. It is very difficult to find other companies to produce substitutes if the situation mentioned above occurs. So the US Department of Defense hopes that suppliers can leave information about their products in some form to ensure that they can be quickly produced by other manufacturers once they are bankrupt.

Obviously, the original design documents are obviously not handed over, which involves trade secrets and intellectual property issues in the United States. So the US Department of Defense came up with a compromise method - the language that describes the hardware, which is VHDL. Through VHDL, suppliers should describe the behavior of their own integrated circuit chips: for example, what kind of signal is added and how much time it can output. In this way, if it is necessary for other manufacturers to produce substitutes, they only need to design the same chip as the VHDL document. Such substitutes are equivalent to the independent design of new manufacturers without understanding the original product structure, so it is not likely to involve knowledge infringement.

Verilog HDL was also formed in the same era and was developed by Gateway Design AutomaTIon around 1983. Its architecture is similar to VHDL, but is mainly used for hardware emulation. Perhaps private companies are more practical, Verilog is much more compact than VHDL.

Thus, none of the two most popular languages ​​for circuit design was developed for designing hardware (not to mention the powerful EDA software that is not available in the 1980s). Therefore, when the HDL language standard was originally developed, it was not considered how the code was implemented in hardware. In other words, some code is simple to write, but it can be very complicated to implement or almost impossible to implement.

Third, the comprehensiveness of HDL code

Now go back to the original question. Why do HDL code such as divisions and loops always go wrong?
As can be seen from the previous section, any code that conforms to the HDL grammar standard is a description of the hardware behavior, but not necessarily the design information that directly corresponds to the circuit. Behavior descriptions can be based on different levels, such as system level, algorithm level, register transfer level (RTL), gate level, and so on. With the current comprehensive capabilities of most EDA software, only RTL or lower-level behavioral descriptions are guaranteed to be synthesizable. What many beginners try to do is to let the software synthesize algorithm-level or more abstract hardware behavior descriptions.

For example, to achieve the operation of dividing two variables, if you write C=A/B in the code, you will find that only some simulation software can execute this code correctly in the pre-simulation, but almost any software It cannot be integrated into hardware. Don't blame the software too stupid Imagine if we did our own calculation of division? From the high to the low, the test is repeated, the remainder, and the shift. Triggering and retrieving require a subtractor. The intermediate result of the quotient and remainder must have a register store; this operation obviously cannot be completed in one clock cycle, and a state machine is needed to control the timing. A simple C=A/B is too abstract compared to all of them, and it is really too difficult to implement for EDA software that can only accept RTL or lower level descriptions. And if the code is similar (Verilog)
Always @(posedge clk)
In this way, the division is required to be completed on one clock, which is even more impossible. (Note: Some FPGA software provides multiplication and division arithmetic modules, but it can only support direct calls. It does not support the integration of statements such as C=A/B into division modules.)
Another example is that a common problem for many beginners is to try to make the HDL perform a loop operation, which is the same (Verilog):
For (i=0; i
Parity = parity xor data;
Some simpler integrated software will completely reject the integrated loop statement; while some more powerful software can be integrated only when wordlength is constant; when wordlength is a variable, no software can synthesize the above statement. This is because the hardware scale must be limited and fixed. When the synthesis software encounters a loop statement, it is always expanded into a number of sequential execution statements, and then integrated into a circuit. If wordlength is a constant, the number of expanded statements is deterministic and synthesizable; and if it is a variable, the number of expanded statements is uncertain, and the number of corresponding hardware circuits cannot be determined and cannot be synthesized. It may be said that a variable loop can be implemented with a counter, but this is the same as the division above. That requires extra hardware to store intermediate results and timing control. The loop statement like the above is too abstract to describe, and the software can't accept it.

Fourth, how to judge the code written by yourself is synthesizable?

Summarize in a simple sentence: the computer is never smart. In particular, the general ability of EDA software to integrate HDL code is always worse than people. For a piece of code, if you can't imagine a more straightforward hardware implementation, then the EDA software will definitely not work. For example, adders and multiplexers are circuits that everyone is familiar with, so operations like A+BC, (A>B)?C must be integrated. The more complex operations such as division, rooting, and logarithm must be implemented by certain algorithms. Without an intuitive and simple implementation method, it can be judged that those calculations cannot be integrated, and they must be written more specifically according to their algorithms. The code can be implemented. In addition, the description of the behavior that the hardware cannot support can of course not be integrated (for example, the double-delay trigger logic like DDR memory is implemented on the FPGA, the code is easy to write, but it cannot be implemented).

However, such a standard of judgment is very subjective and vague, and it is up to the designer's own experience to judge the specific situation. If you want a relatively objective standard, generally speaking: in the description of the RTL level, all logical operations and addition and subtraction operations, and their finite sub-combinations, are basically synthesizable, otherwise there is a possibility that they cannot be integrated. . Of course, such standards are still flawed, and EDA's technology is constantly evolving. In the past, code that could not be integrated may be in the future. Some software that does not support software may be replaced by software. For example, a fixed number of loops, multiplication with a constant parameter, etc., some EDA software supports the synthesis of them, and some software does not.

Therefore, the correct judgment still depends on practice to accumulate experience. When you can more accurately determine the synthesizable nature of the code, your mastery of HDL is completely introductory.

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