System Generator is a design tool developed by Xilinx for digital signal processing. It can perform fixed-point simulation in Simulink by embedding some modules developed by Xilinx into Simulink library, but setting the type of fixed-point signal, so that you can compare The difference between fixed-point simulation and floating-point simulation. And you can generate HDL files, or netlists, which can be called in ISE. Or directly generate a bitstream download file. Can accelerate the development of DSP systems.

Simulate with System Generator

1, must include modules: Gateway In, Gateway Out, System Generator, and Xilinx fixed-point arithmetic unit.

2. For external interface modules with precise clock limits in system design, using System Generator design is not the best method. In this case, you can use HDL and other methods to implement, and then import the Black Box provided by System Generator tool into Sysgen project.

System Generator Blockset

1, mainly includes: Xilinx Blockset, Xilinx Preference Blockset and Xilinx XtremDSP Kit three library function blocks.

2. Xilinx Blockset contains all the modules for building digital signal processing systems and other FPGA digital systems in Simulink.

3. Xilinx Preference Blockset is a higher level module, which is composed of modules in Xilinx Blockset, which reduces development difficulty and has high reliability.

Signal data type

1. The output format of Xilinx Block can be set to: Full precision and User-defined precision.

Full precision: automatically performs bit width expansion in the operation

User-defined precision: Wrap or saturate the output (user settings).

2. In System Generator, click Format –> Port/Signal Displays –> Port Data Type to display the data type of each module's input and output.

3. When Simulink cannot determine the data type and sampling rate, it will report an error. Usually this happens when there is feedback. At this point, the signal can be forced or redefined by adding an Assert module. It does not occupy hardware resources.

4. Gateway In can set the Sample Period. The larger the value, the fewer the sampling points. In general, for the same set of Gateway In, the sample period should be the same, ie the sampling rate is the same. So when modifying a Sample In of Gateway In, remember to update the Sample Period of the same level of Gateway In at the same time.

5. Sample rate conversion, using modules: Up sample and Down sample. Different colors in System Generator represent different sampling rates. Click on Format –> Sample TIme Colors

Generate test vectors using Matlab

1. Generate a test vector using the From Workspace block. Note that the data must be a 2xn matrix:

Colume 1 = TIme values

Colume 2 = data values

For example: [1:101; sin(2*pi*[0:.01:1])]

2. Use the To workspace block to output sysgen data to MATLAB for analysis.

Clock cycle

1. Simulink system period is the Simulink simulation clock cycle, which must be the largest common factor of all sampling periods in the design. For example, there are 3 sampling periods (2, 3, 4) in the system, then the Simulink system period is 1.

2. If the FPGA system clock cycle is 10 ns, then the Simulink system cycle, 2s, 3s, 4s three sampling periods correspond to 10ns, 20ns, 30ns, 40ns when the FPGA device is implemented. Another approach is to define the Simulink system cycle as the system cycle of the FPGA, which eliminates the conversion between clock cycles.

3. The Clock Enable Probe module can be used to implement the potential clock enable signal.

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