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In the design of system-on-chip (SoC), MIPS' RISC processor is a widely used embedded CPU with high performance and low power consumption, which can be easily integrated into a complete system on chip. This allows developers to focus on the design of user IP modules. The MIPS architecture processor occupies a leading position in the CPU architecture market for digital set-top box microprocessors and decoders. Among the MIPS family's products, the 32-bit 4KcTM processor is a representative one that uses the MIPS32 CPU architecture and supports the MIPS IITM instruction set. In the SoC system design described in this article, the MIPS32TM4KcTM processor is used as the CPU core of the chip.

In the current digital consumer electronics market, HDC chips based on the SoC platform are the core components of all digital TV reception and playback devices. The SoC chip is specific to the HDTV decoding system, which is a function module such as MPEG-2 demultiplexing (DeMux), audio and video decoding (AVD), video format conversion (VTP), picture post processing (OSD), and interface I/O control. Integrated on a single chip. To integrate a number of complex system control modules and user IP modules onto a single chip and enable them to work together, the interface between the various modules must be designed. In this paper, the design scheme of the system bus interface module (HIF) is proposed for the project of high-definition digital TV SoC platform, and the simulation experiment is carried out.

The main function of the HIF module in the system

The HDTV-SoC platform is a powerful and complex system. This paper focuses on the design of the on-chip bus controller in the SoC architecture. The on-chip bus provides a flexible and versatile integration method for specific applications. It requires a simple structure and fast speed to achieve multi-resource interconnection in a single chip. The bus structure of the HDTV-SoC system is shown in Figure 1. It is divided into three levels, namely the EcInterface, the system bus and the peripheral bus that interface with the MIPS processor. It can be seen from Fig. 1 that the location of the HIF module in the system is very critical. It is the interface unit between the system bus (Host Bus) and each IP module and peripheral I/O modules, namely the system bus and the peripheral bus. The bridge between the two plays a role of “taking the front and the back” in the system, and is an important channel for data exchange between the CPU and the external module. Specifically, the HIF module mainly performs three major functions, namely, setting of the external module W/R register and reading of the status register, reading and writing control of the external module dual port RAM, and control and management of the external module interrupt.

Figure 1 HDTV - SoC system block diagram

Circuit function module design

As can be seen from the above, the HIF circuit design is mainly divided into three modules: a register read/write module, a dual port RAM read/write module, and an interrupt processing module.

Register read and write module

An important way to exchange data between the CPU and the external module is to control and initialize the functions of the external module through the reading and writing of registers. The system bus reads and writes the register resources inside the HIF module according to the specified timing. Each bit of these registers is directly connected to the external module in a wired manner. After receiving the address and data coming from the system bus, the HIF module first performs address decoding, selects the corresponding register, and then writes the data. Figure 2 is a logical block diagram of the module.

Figure 2 Register read and write module block diagram

MIPS' 4Kc processor supports burst operation. The so-called burst operation means that after the first address is given, multiple read and write operations can be performed continuously without having to give the corresponding address for each operation. On the bus, a burst instruction takes just one clock cycle, just like a single operation instruction. When processing the burst operation, the HIF module converts a burst instruction into four single-cycle instructions. After the conversion, it is ensured that the write data coming from the bus is synchronized with its corresponding instruction. Thus, during burst operations, the write data and instructions seen from the perspective of the register bank occur simultaneously, although this is not the case. To achieve this burst operation, a FIFO mechanism must be introduced. The depth of the FIFO is 4, which is consistent with the burst length supported by the 4Kc processor. The FIFO is cleared after a system reset and can receive burst data on the bus at any time. When the system is working properly, the FIFO module indicates the input and output data through the "in" and "out" pointers respectively to track the usage of the FIFO. The FIFO also needs to use a "bypass" signal to determine whether to bypass the module. This occurs in the case of a single instruction operation (bypass='1'), at which point the data bypasses the FIFO and goes directly to the register. The logic block diagram of the FIFO mechanism is shown in Figure 3.

Figure 3 FIFO mechanism logic block diagram

Dual-port RAM read-write module <br> In terms of interface logic with the system bus, the RAM read-write module is similar to the register read-write module, and will not be described here. The difference lies in the interface logic with the external module. The register read/write module uses direct connection, while the RAM read/write module must meet the corresponding interface timing of the dual-port RAM. In this design, a dual-port RAM unit of SMIC's 0.18 μm library was selected as the model. The interface timing of this model is shown in Figure 4, including both read timing and write timing.

Figure 4 Dual port RAM interface timing diagram

Interrupt Control Module The Interrupt Control Module is responsible for handling interrupts issued by interrupt sources such as DeMux, VD, GPIO, etc. For the system, how to make the generated interrupts get a response as soon as possible is a key issue. The connection of the interrupt pins provided by the MIPS 4Kc processor can be seen in Figure 1. The description of the pins is shown in Table 1 [1].

Table 1 MIPS 4Kc processor interrupt pin description table

It is customary to connect the SI_TimerInt signal to the SI_Int[5] pin, as shown in Figure 1. Thus, the external interrupt pin of the 4Kc processor has five remaining, namely SI_Int[4:0]. In this design, the external interrupts of the system are divided into five levels, and the priorities are ranked from high to low according to the order of SI_Int[0] to SI_Int[4]. For each external module, all its interrupt sources are also divided into 5 levels, reflecting that the output of each module is a 5-bit register XInt[4:0], and likewise, according to XInt[0] to XInt[5] The order interrupt priority is ranked from high to low. Assuming that the system has N external modules, the input of SI_Int is obtained between the XInt outputs of each module. These logics are implemented in the TopInt module, as shown in Figure 5.

Figure 5 TopInt module internal logic

It should be noted that the TopInt module itself is also treated as an external module of the system, and the system can perform the same register read and write operations as other modules. In this way, when the CPU processes an external interrupt, it can trace the source of the interrupt by reading the contents of the XIntn register. In addition, within each external module, five 32-bit interrupt request registers IRQREG0~IRQREG4 and five 32-bit interrupt mask registers MSKREG0~MSKREG4 are set. When a bit in the MSKREGn register is set to "1", the interrupt of the corresponding bit in the IRQREGn register is masked. In each of the IRQREGn registers, the 32 bits are phased or the value of the nth bit in the corresponding XInt register of the module is obtained. It can also be seen that the interrupt priority is from high to low in the order of IRQREG0 to IRQREG4. The logical relationship between them is shown in Figure 6.

Figure 6 External module interrupt register logic

In addition, all of these registers are addressed in the module for easy access by the CPU. In this way, for any interrupt, the interrupt source that generates the interrupt can be known by querying the CPU at most twice.

Simulation and synthesis

The simulation work of the design is carried out in two parts. Each module is first simulated separately, and the modules are adjusted after the waveform is correct. When TESTBENCH is programmed, different work situations are handled in different files. Specifically to the HIF module, the simulation mainly completes the verification of the following aspects: writing and reading of registers, writing and reading of dual-port RAM, and generation and acquisition of interrupts. In the design, the code is written in VHDL, and the ModelSimSE5.7 tool from Mentor is compiled and simulated. During the simulation, the dual-port RAM model provided by the SMIC library is attached to the system as an external module, and the interface timing of the model is exactly the same as that shown in FIG. Figure 7 shows the simulated HIF module simulation waveform.

Figure 7 HIF module simulation waveform

Since the design work of the entire SoC system is still in the FPGA verification stage, the XST synthesis tool included in the ISE6.1 software of Xilinx is selected in the synthesis, and the XCV2000E of the Virtex-E series is selected for the FPGA device. The combined results report is shown in Table 2.

Table 2 Comprehensive Results Report Form

to sum up

It can be seen from the simulation and comprehensive experimental results that the design of the HIF module can meet the functional requirements of the system, and the area of ​​the FPGA and the proportion of resources occupied by the integrated module are very small, and some can even be neglected. It will not affect the design and implementation of other modules in the system. The integrated main operating frequency is 116.959MHz, which fully meets the design requirements.

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