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Design engineers in handheld devices such as cell phones, digital cameras, MP3 players and PDAs are continually facing the challenge of reducing the cost of the entire system while providing more functionality in a smaller footprint. IC design engineers are driving this trend by reducing the size of the silicon space while increasing the speed and performance of the device. To optimize functionality and chip size, IC design engineers are constantly minimizing feature size in their designs. However, what is the price? The reduction in IC functional size makes the device more susceptible to ESD voltage damage. This trend has an adverse effect on the reliability of the end product and increases the likelihood of failure. As a result, handheld design engineers face the challenge of finding a cost-effective ESD solution that clamps the voltage to a lower level so that those ICs that are increasingly sensitive to ESD are used. The end products maintain high reliability.

ESD waveform

The most common waveform used to define a typical ESD event in a system-level manner is the IEC61000-4-2 waveform, which is characterized by its sub-nanosecond rise time and high current level (see Figure 1). The specification of this waveform requires a four-level ESD level. Most design engineers require products to be limited to the highest level of 8kV contact discharge or 15kV air discharge. When performing component-level testing, the contact discharge test is the most suitable test method because the air-discharge test cannot be repeated on such small components.

ESD considerations

The purpose of the ESD protection device is to reduce the ESD input voltage of thousands of volts to a safe voltage that the protected IC can withstand and bypass the current from the IC. Although the input voltage and current of the required ESD waveform have not changed over the past few years, the safe voltage level required to protect the IC has decreased. In the past, IC designs were more robust in terms of ESD protection and were able to withstand higher voltages, so there was plenty of room to choose when choosing a protection diode that meets the requirements of IEC61000-4-2 Level 4. For today's ESD-sensitive ICs, design engineers must not only ensure that the protection device meets IEC61000-4-2 Level 4 standards, but also ensure that the device can clamp the ESD pulse to a low enough level to ensure The IC is not damaged. When choosing the best protection for a given application, design engineers must consider how low the ESD protection device can control the ESD voltage.

Figure 1: List of IEC61000-4-2 specification indicators.

Choose the most effective protection solution

The key DC metrics for protection diodes are breakdown voltage, leakage, and capacitance. Most data pages also describe the maximum rated voltage of IEC61000-4-2, which means that the diode will not be damaged by ESD strikes at this voltage. The problem is that most of the data pages do not have any information on the clamping voltage for high frequency, high transient currents like ESD. However, it is not a simple matter to specify the clamp voltage in the IEC61000-4-2 specification. This is because the original intention of the specification is to verify that the system is qualified and the frequency is so high. To test this protection against the protection device, it is critical not only to check if the protection diode is qualified/failed, but also to check how low the ESD voltage can be clamped.

The best way to compare the protection diode clamping voltage is to use an oscilloscope to capture the actual voltage waveform across the protection diode during ESD generation. When observing the voltage waveform of an ESD protection device subjected to the IEC61000-4-2 standard test, usually the initial voltage peak immediately follows the second peak and the final voltage will stabilize. The initial peak is caused by the combination of the initial current peak of the IEC61000-4-2 waveform and the overshoot caused by the inductance present in the test circuit. The duration of the initial peak is very short, thus limiting the energy delivered to the IC. The clamp performance of the protection device is shown on the graph, which is after the first overshoot. The second peak should be focused on, because the duration of the peak is longer and the energy consumed by the IC under test will increase. In the discussion that follows, the clamp voltage is defined as the maximum voltage of the second peak.

Comparison of several protection diodes

For a fair comparison, the selected components should have similar package dimensions and parameter specifications. For comparison, three ESD protection diodes are considered to be interchangeable when comparing their electrical characteristics. These devices are bidirectional ESD protection devices with the same breakdown voltage (6.8V), capacitance (15pf) and package outline (1.0 x 0.6 x 0.4 mm). The products selected here are competitor 1 RSB6.8CS, competitor 2 PG05DBTFC and ON Semiconductor's ESD9B5.0ST5G.

When comparing the DC performance of the above devices, the results appear to be the same (see the curve shown in Figure 2). In addition, they all claim to comply with IEC61000-4-2 Level 4, which means they will all withstand ESD strikes up to 8kV contact voltage.

Figure 2: Comparison of DC characteristics of three ESD devices.

To compare the clamping performance of each device, an oscilloscope is used to capture the voltage waveform during the ESD. The above devices were tested side by side using the exact same test conditions. The response of each diode to positive/negative ESD pulses is shown in Figure 3. The input pulse used is the standard contact voltage (8kV) of IEC61000-4-2 level 4.

Figure 3: Clamping voltage comparison of three ESD protection diodes (oscilloscope screen shot).

As can be seen from the graph shown in Figure 3, it is clear that the ON Semiconductor protection solution (black waveform) provides a lower ESD pulse clamp voltage than two competitors' devices (blue waveform). Compared to KEC's 18V and Rohm's 23V, ON Semiconductor's devices clamp positive pulses to 14V. During the negative pulse, the difference in clamping voltage between the three devices is more pronounced. The clamping voltages of the devices for ON Semiconductor, Competitor 2, and Competitor 1 for the negative pulses are 20V, 34V, and 42V, respectively. There is a clear distinction between these three devices during negative ESD. The clamping voltage of the competitor 2 device is 70% higher than that of the ON Semiconductor device, while the clamping voltage of the competitor 1 device is the two of the ON Semiconductor devices. More than double. The remaining negative pulse voltage after a competitor's protection device is potentially dangerous for new IC designs that are more susceptible to ESD damage. However, ON Semiconductor's devices maintain a low clamping voltage in both the negative and positive pulses, keeping the risk of damage from positive/negative ESD pulses to a minimum.

Good protection devices require good clamping of positive/negative ESD pulses to ensure the highest reliability of the end product under realistic conditions. The low clamping voltage in both positive and negative directions ensures that the device protects extremely sensitive ICs, allowing designers to take advantage of the latest IC technologies that enable more features and higher speeds. ON Semiconductor's protection devices not only enable the IC to withstand ESD strikes, but also provide the lowest clamping voltage on the market. Recognizing that clamping voltages are becoming increasingly important when selecting ESD protection devices, ON Semiconductor offers clamping characteristics similar to those in Figure 3 in the data sources of the latest protection devices.

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