In front of the innovation network user Ricky Su sent a blog post "Talk about the black box in the FPGA (BlackBox)", learned to feel good use, recently found an article on the Internet to talk about this aspect, I feel that the writing is very good To share with you, the article is as follows: Module my_comp(input [3:0] i1, input [3:0] i2, output [3:0] o1 ); This is a relatively large module. I can see it at a glance. Then build the project in ISE, import the module, as a design file, the complex design process is similar. Then run XST for synthesis. After the integration is complete, look at the project directory and you will find the NGC file. This NGC file is encrypted in binary, so you don't have to bother to study it. Even if you can convert it to edif format with ngc2edif, for complex designs, getting edif can't restore its original logical intent. So far, we have obtained the NGC format encrypted design file. Note that when making NGC, it is necessary to prevent the inclusion of PAD or IOB, because our NGC is to be called by other projects, which means that the NGC screw must be placed in any position, and once we put the PAD And the IOB is also included, then the NGC will only be placed at the boundary interface of the customer project, which is the opposite of the actual situation. The actual situation of our NGC is only a part of the internal, which causes the final P&R failure of the customer project. Ok, now let's say that other projects (our customer projects) need to call this cryptographic module. What should we do? Module my_comp(input [3:0] i1, input [3:0] i2, output [3:0] o1 ); Endmodule It's okay to remove the intermediate implementation. Let me give you an example of a customer project. Module my_comp(input [3:0] i1, input [3:0] i2, output [3:0] o1 ); My_comp u1 ( The code of the customer project, together with the black box code we created, is loaded into the ISE project, and then run XST synthesis to get the netlist of the new project. Of course, because we provide the black box, the corresponding design result It is still a black box. So when do you want to replace the black box? At this stage, it is time to really replace the black box. In fact, it is very simple to do. Next, run implementaTIon, you will find that all the way is working, it's so cool~ Capillary Manometer,Capillary Tube Manometer,Capillary Thermometer,Vacuum Manometer ZHOUSHAN JIAERLING METER CO.,LTD , https://www.zsjrlmeter.com
This method is actually very simple. Give an example.
First write the module with HDL, such as:
Assign o1 = (i1 > i2)? i1: i2;
Endmodule
To prevent NGC from having IOB and PAD: Find Synthesize-XST in ISE, then right-click on the property and disable the following two items in the category's Xilinx Specific OpTIons.
- iobuf Add I/O Buffers
- iob Pack I/O Registers into IOBs (this can be NO)
First, the encrypted module is binary and cannot be used in combination. Our method is to make an equivalent black box. The so-called black box is actually a module that only has an interface and is not implemented. For example, the black box in the above example is like this.
.i1 (i1 + 4'h1),
.i2 (i2 + 4'h2),
.i1 (i1),
);
Endmodule
We put the generated NGC file in the working directory of the client project - the work is done.
When the P-R is in progress, the final black box replacement is performed. ISE will try to find a black box replacement in the working directory or other specified path, so we put the NGC in the working directory.